Advances in semiconductor fabrication technology have allowed Very Large Scale Integration (VLSI) and Ultra Large Scale Integration (ULSI) chips, having up to several million devices thereon, to be reliably and economically produced. As device densities increase and device sizes shrink, system performance is becoming more limited by the interconnection and packaging of the chips, and not by the internal circuitry of the chips themselves. For example, package limitations such as the maximum allowed number of chip input/output pads, have resulted in the inability to utilize all of the chip's capabilities. Multi-chip packaging generally requires wide spacing of chips to accommodate wiring channels, which results in longer wiring distances for chip interconnection, and leads to increased parasitic capacitance and a decrease in system speed. Moreover, complex packaging structures are inherently expensive and unreliable.
One high density packaging technique for integrated circuit chips is the multilayer ceramic substrate which is described, for example, in U.S. Pat. No. 3,993,123 to Hugh, et al. The multilayer ceramic substrate provides interconnections for about 100 integrated circuit chips and includes up to 33 internal wiring layers and about 1800 brazed input/output pins for connecting to a next level of packaging. Unfortunately, the multilayer ceramic substrate is extremely expensive to fabricate, and the fabrication methods employed limit the density of the substrate's internal wiring. Furthermore, the reliability of the chip to ceramic substrate interconnections (generally solder bumps or balls) degrades when small, high density interconnections are used because of thermal mismatches between the chips and substrate. Internal defects within the substrate wiring cannot be repaired once the substrate has been fabricated, so that additional engineering change (EC) wiring and pads must be included to provide acceptable yields.
One attempt to overcome the limitations of multilayer ceramic substrate technology has employed multilayer thin film wiring layers on top of a multilayer ceramic substrate. For example, U.S. Pat. No. 4,617,730 to Geldermans et al. provides thin film fine line metallization on one side of a support substrate. While thin film wiring layers may provide high density wiring for at least some of the chip packaging, the resulting structure is complex and costly. Furthermore, by forming the thin films on the substrate, the yield loses in the thin film layers are added to the yield losses in the substrate, thereby lowering overall yield. The underlying substrate also increases weight. Thin film technology has also been employed without the multilayer ceramic substrate in an attempt to provide improved packaging for integrated circuit chips. This technology employs thin film metallization techniques, similar to those employed on the chips themselves, for chip interconnection and packaging. One example of thin film technology for packaging is described in U.S. Pat. No. 4,714,516 to Eichelberger, et al., in which a thin film multilayer wiring structure is sequentially formed over a plurality of fully formed integrated circuit chips disposed adjacent one another on an underlying substrate. The thin film structure comprises alternating layers of polymer insulator and metal, which are formed, layer by layer, over the integrated circuit chips. Unfortunately, by forming the thin films on the chips, the yield losses in the thin film layers are added to the yield losses in the chips themselves, thereby lowering the overall yield of the whole. The package cannot easily be tested until it is fully completed, and the underlying substrate increases weight and makes heat removal more difficult. Furthermore, cycle time for completing the package is impacted because the chips and thin films cannot be produced in parallel. The crude alignment of the chips with respect to one another dictates that each and every grouping of chips needs to be mapped so the discretionary or individually customized interconnection patterns may be made by software driven, direct write techniques.
Yet another attempt at using thin film technology is disclosed in "Active Silicon Hybrid Wafer Scale Packaging" by Richard C. Jaeger (SRC Technical Report No. T86046, June 1986) in which pre-tested integrated circuit chips are mounted onto holes etched in a silicon wafer and conventional multilayer thin film metallization links are built to connect the chip pads to interconnection lines prebuilt in channels between the chips on the silicon wafer. Like the Eichelberger et al. patent, this approach requires customized links and discretionary lithography to align the chips to the wafer. Finally, the wiring channels are limited to the spaces between the chips, decreasing density and wiring capability.
Decal technology has also been employed in an attempt to provide improved integrated circuit packaging. In this technology, a thin film decal is formed on a first surface, and then transferred onto a chip or packaging substrate. One attempt to use decals for chip interconnection is disclosed in U.S. Pat. No. 4,755,866 to Marshall, et al. in which an array of high density chips include a plurality of decals, each of which overlies a single chip and part of the adjacent chip. The chips are directly connected to a frame or heat sink. Unfortunately, the use of multiple decals creates alignment, assembly and repair problems.
Wafer Scale Integration (WSI) technology has attempted to overcome many of the limitations of high density packaging by wiring circuits to the fullest possible extent on a processed substrate (a wafer). WSI has not been a commercial success, notwithstanding a large industry investment, because integrated circuit yields decrease dramatically as circuit count increases. Elaborate redundancy schemes have been devised for yield improvements, but these redundant circuits tend to eliminate the economic and performance advantages of WSI. Furthermore, in order to utilize the larger number of circuits on a wafer, additional wiring levels for long range signals need to be fabricated on the wafer, which further degrades yield and impacts the time to make a complete package.
The above survey indicates that the art has yet to find a low cost, lightweight, fast, dense and reliable packaging technique for integrated circuit chips.